1. Field of the Invention
The present invention relates to a method for the control of wafer surface temperatures of wafers which carry integrated circuits. More particularly, the invention is directed to a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates employed in the fabrication of semiconductor devices.
2. Discussion of the Prior Art
Numerous publications in this technology address themselves in varying degrees of applicability to the problem of controlling wafer surface temperatures, for example, during the post exposure baking of integrated circuit-carrying wafers for semiconductor devices.
Maeda, U.S. Pat. No. 5,626,782 is directed to a post exposure baking apparatus for forming fine resist integrated circuit line patterns on semiconductor wafers. In particular, this patent provides a capability for an evaluation in the changes of linewidth, and calculation methods for the temperatures in order to obtain desired linewidths for the integrated circuits, and for this purpose incorporates a plurality of heating pins which are independently temperature-controlled.
Marchman, et al., U.S. Pat. No. 5,656,182 is directed to a process for fabricating a device wherein control is provided by a near-field imaging latent effect which is introduced into energy-sensitive resist material. This effects a control over resist process parameters, wherein one of the parameters relates to the post-exposure baking.
Hobbs, et al., U.S. Pat. No. 5,516,608 is directed to a method for controlling line dimensions formed in a photolithographic process. The method employed in this patent consist of in implementing a measurement of an exposed pattern during the pattern development, and enables a real-time in-line control over critical dimensions for positive-tone chemically implied photoresist systems.
Tani, et al., U.S. Pat. No. 5,252,435 discloses a method for forming a pattern of integrated circuits on a substrate such as a wafer or chip through the intermediary of a high contrast pattern formed by the use of a post-exposure baking step in photoresist processing.
Although all of the foregoing patents to varying degrees direct themselves to different aspects of providing a control over the precision in the size and width of the line pattern for the formed integrated circuits, and also over the control of the semiconductor wafer surface temperatures during the post exposure bake step, there is no disclosure of the unique inventive feedback control concept which may be employed with the use of the in situ surface temperature-adjustable or controllable hot plate, as described in commonly assigned co-pending application Serial No. 09/361,451 (Attorney Docket No. BU998-223; 12235), the disclosure of which is incorporated herein by reference.
At this time, large hot plates, which are ordinarily obtainable from laboratory supply companies, are frequently incompatible with modern lithographic processing employed in the production of semiconductor devices, and the need for the precise control of all steps during the implementation of such processes. In essence, various processes of this type employed in the technology require; for instance, an extremely fine degree of precision to be applied in the temperature control of the post exposure bake step of the baking wafers which have integrated circuits formed thereon. Moreover, in the semiconductor production technology, wafers have become progressively larger in size, and consequently necessitate the utilization of ever larger hot plates. Such considerably larger hot plates are subject to both spatial and temporal non-uniformities which render them unsuitable to applications for lithographic processing. It is also well-known that temperature uniformity during lithographic processing, and particularly during the post exposure bake process step, such as temperatures ranging across the surface of the wafers located on the hot plates, directly affect image size uniformity in integrated circuits formed in lithographic processes employing chemically amplified resist system during the fabrication of semiconductor devices. Thus, any modulation in post exposure bake temperatures can readily change the resultant device image size to a significant degree; for instance, up to about 10-20 nm per degree C.
Accordingly, the present inventive concept relates to incorporating repeating images within a semiconductor wafer integrated circuit line pattern (kerf or functional), to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process. The data is then mapped with regard to image size versus hot plate position, and individual heating zones of the hot plate are adjusted in their temperature for maximum degree of image size uniformity and ultimately attaining optimal device speed and pattern line processing uniformity control.
Basically, the present invention is directed to a method for attaining optimum integrated circuit image size uniformity control for use during integrated circuit fabrication, which includes providing a hot plate having locally adjustable temperature control means; positioning a semiconductor wafer, having a chemically amplified resist system photolithographic pattern thereon, on the hot plate; thereafter developing the wafer; measuring the image linewidth at a plurality of locations across the surface of the wafer; mapping and correlating the obtained image linewidth measurements with known post exposure baking temperature versus linewidth data; and adjusting the hot plate temperature in order to maximize integrated circuit linewidth uniformity.
With regard to the foregoing, it is also contemplated that the invention provides a method for controlling image size using a temperature zone-controllable hot plate such as described in the above-referenced co-pending U.S. patent application Ser. No. 09/361,451, by referring to a specific graphical plot for a specified semiconductor structure which is being fabricated; ascertain information regarding the temperature dependence of the image size, which is essentially linear over a short temperature range; obtaining across the wafer, in each zone, image size data for previously processed lots of wafers; subtracting the desired image size from the previously processed lots for each zone of image size data so as to form a matrix of image size deviations from nominal across the wafer in each zone, (this accounting for any systematic effects of image size control so that this can be later compensated for by temperature control); thereafter calculating the temperature delta (xcex94T) from a nominal value required for each zone by dividing each element in the image size deviation in matrix by a plotted graphical slope which is derived from the temperature dependence graph in order to determine the necessary temperature correction for each zone; and retrieving temperature setpoint versus zone image size data for previously run wafer lots, and subtracting the temperature correction for each zone, so as to result in a matrix of zone setpoints which are transmitted to the hot plate zone temperature controller for current lot or wafer processing.
On the basis view of the foregoing, the hot plate zone temperature controller receives a matrix of setpoints and current zone temperature information, and then adjusts the energy or power applied to each zone in order to achieve the targeted temperature for each zone. This method enables each zone to be imparted a personalization or individualization of the hot plate temperature adjusting process in order to compensate for prior wafer processing non-uniformities; for instance, as regards non-uniform resist thickness, underlying thin film nonuniformity, and the like.
Accordingly, it is an object of the present invention to provide a novel method for controlling wafer surface temperatures during post exposure bake employed in the lithographic processing of semiconductor devices.
Another object of the invention resides in the provision of a novel method for obtaining optimal image size uniformity control employed in the fabrication of integrated circuits on a semiconductor wafer through the intermediary of controlling the post exposure bake temperature of a hot plate supporting the semiconductor wafer.
Yet another object of the present invention resides in the provision of a method of controlling temperatures of individual zones of a hot plate supporting semiconductor wafers employed in the post-exposure baking step in the formation of integrated circuits so as to implement corrective action in order to obtain uniformity and integrated circuit linewidth and thickness during manufacture thereof, through feedback information received on the basis of prior temperature controls applied to precedingly processed wafer lots.